Field of the Invention
The present invention relates to pattern forming apparatuses, mark detecting apparatuses, exposure apparatuses, pattern forming methods, exposure methods and device manufacturing methods, and more particularly to a pattern forming apparatus and an exposure apparatus that are used when manufacturing electron devices such as semiconductor devices and liquid crystal display devices, or the like, a mark detecting apparatus that can suitably be used in the pattern forming apparatus or the exposure apparatus, a pattern forming method and an exposure method that can suitably be used when manufacturing the electron devices, and a device manufacturing method in which the pattern forming method or the exposure method is used.
Description of the Background Art
Conventionally, in a lithography process for manufacturing electron devices (microdevices) such as semiconductor devices (such as integrated circuits) and liquid crystal display devices, exposure apparatuses such as a projection exposure apparatus by a step-and-repeat method (a so-called stepper) and a projection exposure apparatus by a step-and-scan method (a so-called scanning stepper (which is also called a scanner) are mainly used.
Meanwhile, in a lithography process for manufacturing semiconductor devices or the like, multilayer circuit patterns are overlaid and formed on a wafer, and when the overlay accuracy between the layers is poor, the semiconductor devices or the like do not achieve predetermined circuit characteristics, which results in defectives in some cases. Therefore, normally, a mark (alignment mark) is arranged in advance in each of a plurality of shot areas on a wafer and the position (coordinate value) of the mark on a stage coordinate system of an exposure apparatus is detected. After that, based on position information of the mark and known position information of a pattern (e.g. a reticle pattern) that is newly formed, wafer alignment is performed in which the position of one shot area on the wafer is aligned with the pattern.
As a method of the wafer alignment, global alignment in which the position of each shot area is aligned by detecting alignment marks of only several shot areas (which are also called sample shot areas or alignment shot areas) on a wafer to obtain regularity of the array of the shot areas has been mainly used, in consideration of throughput. In particular, recently, the Enhanced Global Alignment (EGA) in which the array of shot areas on a wafer is precisely computed by a statistical method has been a mainstream (e.g. refer to Kokai (Japanese Unexamined Patent Application Publication) No. 61-044429).
However, the requirement for overlay accuracy is gradually getting stricter to cope with finer integrated circuits, and also in the EGA, in order to increase the computation accuracy, it is becoming essential to increase the number of sample shot areas, that is, to increase the number of marks to be detected.
Further, the wafer surface is not always flat due to, for example, ununiformity of resist film thickness, undulation of a wafer, or the like. Therefore, in a scanning exposure apparatus such as a scanner in particular, when transferring a reticle pattern on a shot area on a wafer by a scanning exposure method, a so-called focus-leveling control is performed, in which position information (focus information) in an optical axis direction of a projection optical system of the wafer surface at a plurality of detection points set within an exposure area, on which an image of the reticle pattern is projected via a projection optical system, is detected using a multipoint focal position detecting system or the like, and based on the detection results, the position in the optical axis direction and the tilt of a table or a stage that holds the wafer is controlled so that the wafer surface is conformed to an image plane of the projection optical system within the exposure area (or, so that the wafer surface is within a range of a depth of focus of the projection optical system) (e.g. refer to Kokai (Japanese Unexamined Patent Application Publication) No. 06-283403).
However, since the increase in the number of sample shot areas in the EGA described above causes the decrease in throughput of the exposure apparatus, it is practically difficult to employ the measures of merely increasing the number of sample shots.
Further, in conventional exposure apparatuses, a wafer alignment (mark detection) operation and a detection operation of focus information are independently performed without taking the relation between both operations into consideration, because the purposes of both operations are different.
However, it is certain that integration of semiconductor devices becomes much higher and accordingly circuit patterns to be formed on a wafer become finer in the future, and therefore further improvement of apparatus performance to realize formation of the finer patterns and further improvement in the throughput are required for the exposure apparatus that is a mass-production apparatus of semiconductor devices.